microchip off-campus drive for freshers 2015-2016 candidates on Trainee Engineer - IT and Government Jobs @ career updates latest

Thursday, 1 October 2015

microchip off-campus drive for freshers 2015-2016 candidates on Trainee Engineer

microchip recruitment drive on Trainee Engineer (Design ,Verification, CAD , Software ) in 2015 freshers , microchip jobs in Chennairequire qualification is B.E in ECE, EEE, E&I; ME and   B.E in CS, IT, ECE; ME in related stream interested candidates apply-online 


Job Requirements
1.For Design, Verification, Physical design, Hardware job position
2.Streams eligible to appear : B.E in ECE, EEE, E&I; ME in related stream
3.Strong n basic electronics, digital circuits,  logic design etc.

For firmware/software job position
1..Streams eligible to appear : B.E in CS, IT, ECE; ME in related stream
2.SE - Sound understanding of micro controllers, C, data structures & assembly lang


Trainee Engineer: Design - (2 Positions)
1. Micro-architecture and Design
2.Implementation in Verilog, System Verilog, VHDL and Block Level Verification
3. Synthesis
4.Static Timing Analysis and Closure
5.Design for Testability, Power Estimation
6. Mapping design to FPGA and Pre-silicon Validation


Trainee Engineer :  Verification - (2 Positions)
1. Contribute to Block level test case generation.
2.Participate in Block level test environment design & implementation
3.Continuous knowledge accumulation on basic to increasingly complex design blocks such as Memory controllers, Bus interfaces, Networking protocol standards
4.Participate in chip level test environment implementation
5.Participate in test plan creation for block level - moving towards participation in chip level test plan
6. To gain knowledge on various test bench environments using Verilog/System Verilog & and to participate in their development

 Trainee Engineer : CAD (3 Positions)
1. To perform full chip / block level Physical design activities on Complex SOCs (USB Hubs, Wireless audio SOCs etc.) and Mixed signal ASIC’s
2. To perform chip level layout integration, Timing closure, IR drop analysis and chip level verification
3. To perform Physical design automation – includes block IP integration checks, Standard cell validation and support
4.To perform full chip Physical design on 55nm TSMC / Global and work on Low power designs
5.Learn existing Microchip Physical design and methodologies and contribute toward improvements


Trainee Engineer :  Software (2 Positions)
1.Firmware development for different ASICs / Customer product
2. PC Tools development/Software development kits (SDK)
3. Low level device drivers for different peripherals like USB, Ethernet, I2C, SPI, etc.
4.FPGA / Post silicon validation of new core and peripherals
5.Development of  automated validation PC tools & Labview based automation
6.Documentation – Design document, Test plan, Test reports and User manuals.
7. Design and development of customer demo & silicon validation boards