Job Description :
1.In this position, you will be
responsible for design and validation of various DFT features such as Scan,
MBIST, JTAG, BScan, etc. for Intel's leading edge SoC designs.
2.You will work with post-silicon
teams to comprehend their usage models, test time/fault coverage/data
collection goals, and tester capabilities and limitations.
3.You will work with IP and
integration design teams to understand the design and functional-mode behaviors
of the logic and circuits.
4.You will micro-architect DFT
features which are compatible with the specific product/post-silicon
requirements and constraints.
5.You will assist in the RTL and
schematic implementation and pre-silicon validation and debug of these DFT
features.
6.You will also be expected to
deliver high-quality documentation for consumption by the post-silicon teams
who will use the DFT features.
Educational Qualification : B.Tech
Experience : Experienced
Location : Bangalore
Qualifications :
1.B.Tech with 3-5 years of
experience or M.Tech with 0-2 years of experience in VLSI or equivalent.
2.Strong knowledge of DFT
architectures & methodologies. This includes Scan, ATPG, Mbist, BScan, IO
DFx, etc.
3.Proven knowledge of Verilog &
System Verilog, RTL design and micro-architecture skills.
4.Strong knowledge of SoC
tools/methodology (OVM, Saola, ACE, VCS*, Lintra, CDC, Synthesis, Spyglass,
etc).
5.Strong debug skills and
demonstrated experiences in Perl & TCL scripting.
6.Strong Communications skills and
the ability to effectively work with cross functional teams.
